TSYS School Computer Scientist Yi Zhou Publishes Research on Optimizing System Longevity and Performance

New research by TSYS School computer scientist Yi Zhou and his colleagues Hui Sun of Anhui University, Yajie Deng of Northwestern Polytechnical University, and Xiao Qin of Auburn University explains that persistent memory (PM) bridges the latency and cost gap between dynamic random access memory (DRAM) and solid-state drives (SSD). As these researchers add, within the DRAM–PM–SSD hierarchy, deploying key-value-separated key-value stores (KV-separated stores) is imperative for optimizing system longevity and performance. This architecture mitigates SSD write amplification and preserves PM endurance by minimizing writes. According to Zhou et al., existing KV-separated stores in the DRAM-SSD architecture, however, fail to fully exploit this three-tier hierarchy due to three issues. First, LSM-tree indexes incur high read amplification on PM. While learned indexes offer faster reads, they suffer from severe write-read asymmetry that can undermine overall efficiency in write-intensive workloads. Second, the lack of real-time invalid data identification delays space reclamation. Third, contemporary KV stores treat PM as a passive write buffer, underutilizing its low read latency under skewed workloads. To address the above issues, their study proposes PALIKV – a PM resident learned index-based KV store for the DRAM-PM-SSD hierarchy. The researchers first design an adaptive two-level index that combines a PM learned index with a dynamic DRAM B+-tree buffer. As they explain, this structure balances lookup efficiency with high write throughput while filtering redundant updates and extending PM lifespan. Second, their learned index enables real-time invalid data identification that facilitates an expedited garbage collection with device-specific reclamation granularity, thereby significantly reducing space amplification. Third, a hotness-aware data placement proactively migrates warm data from SSD to PM, allowing PM to serve skewed reads and eliminating the latency-constrained SSD from the critical read path. The experimental results presented in Zhou et al.'s study, which is set to appear in a future issue of IEEE Transactions on Computers, unveil that PALIKV significantly outperforms SOTA KV-separated stores and DRAM-PM-SSD KV stores in terms of throughput and latency. Turner Business congratulates Zhou on this achievement, which takes his A-level journal publication count beyond 20.